#
# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: X11
#

#Create the project in the output directory
set_part xcvc1902-vsva2197-2MP-e-S

#Set the board part
set_property board_part xilinx.com:vck190:part0:3.2 [current_project]

#####Read all sources for building the project#####

#Generate the system BD that has only CIPS and DDR NOCs
source ../sources/bd/bd.tcl

#Read the RTL files that has XPM NMUs and NSUs instantiated along with traffic generators and BRAM 
read_verilog {{../sources/rtl/validate_ip_S_AXIS.v} {../sources/rtl/validate_ip_M_AXIS.v} {../sources/rtl/pl_master_to_pl_slave.v} {../sources/rtl/axis_MxN_top.v} {../sources/rtl/pl_to_pl_master.v} {../sources/rtl/pl_to_pl_slave.v} {../sources/rtl/design_1_wrapper.v}}

#Generate the XCI files for BRAMs, Performance Traffic Generators and VIO IPs
source ../sources/ip/axi_bram_ctrl_pl_slave_from_pl_master.tcl
source ../sources/ip/axi_traffic_gen_0.tcl
source ../sources/ip/axis_MxN_vio.tcl
source ../sources/ip/axis_vio_pl_master_to_pl_slave.tcl

#Read the XDC files for creating NoC connection, setting its QoS settings and the aperture of XPM NSUs. 
read_xdc ../sources/xdc/noc_constraints.xdc

#Read the XDC files that has constraints for creating ILAs and for connecting them to debug hub in the design. This constraint is auto-generated by the tool based on "Set up Debug" flow.
read_xdc ../sources/xdc/design_1_wrapper_debug.xdc

#####Set the USED_IN {synthesis_pre} for NoC constraints#####
set_property USED_IN {synthesis_pre} [get_files ../sources/xdc/noc_constraints.xdc]

#####Generate all targets : XCI/BD######
generate_target {synthesis implementation} [get_files design_1.bd]

synth_ip [get_ips {axi_bram_ctrl_pl_slave_from_pl_master axi_traffic_gen_0 axis_MxN_vio axis_vio_pl_master_to_pl_slave} ]

##Updating the sourcefile set 
set_property source_mgmt_mode All [current_project]
update_compile_order

#Validate_noc happens in synth_design call. User can also call it explicitly 
synth_design -top design_1_wrapper -part xcvc1902-vsva2197-2MP-e-S
write_checkpoint -force outputs/dcps/post_synth.dcp

#Place and Route
opt_design
place_design
route_design
write_checkpoint -force outputs/dcps/post_route.dcp
#Device Image Generation and LTX file Generation for debug
write_device_image -force outputs/design_1_wrapper.pdi
write_debug_probes -force outputs/design_1_wrapper.ltx

exit
